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IMAGE SENSOR SOLUTIONS
Register Set (continued)
Register Name
Address
Mnemonic
Type
Reset Value
Digital Video Mode 0
06 Hex
VMODE0
Read/Write
00 Hex
Register Name
Address
Mnemonic
Type
Reset Value
Digital Video Mode 1
07 Hex
VMODE1
Read/Write
00 Hext
Bit
7:6
Bit Symbol
PixDataSel
Description
Use to program the number of
7
Bit
Bit Symbol
PixClkMode
Description
Assert to set the pclk to “data
active bits on the digital video bus
d[11:0] , starting from the MSB
ready mode”. Clear, the default, to
set pclk to “ free running mode ”.
( d[11] ). Inactive bits are tri-stated.:
00
12 bit mode, bits
d[11:0] of the digital
video bus are active.
6
VsyncMode
Assert to set the vsync pin to
“pulse mode”. Clear (the default)
to set the vsync signal to “level
mode”.
01
10
11
This is the default.
10 bit mode, bits
d[11:2] of the digital
video bus are active.
8 bit mode, bits
d[11:4] of the digital
video bus are active.
Reserved.
5
4
HsyncMode
PixClkPol
Assert to force the hsync signal to
pulse for a minimum of four pixel
clocks at the end of each row.
Clear (the default) to force the
hsync signal to a level indicating
valid data within a row.
Assert to set the active edge of
the pixel clock to negative. Clear
5:4
PixDataMsb
Use to program the routing of the
MSB output of the internal video
(the default) to set the active edge
of the clock to positive.
3:0
A/D to a bit on the digital video
bus.
00
A/D [11:0] -> d[11:0].
01
A/D [10:0] -> d[11:1]
10
A/D [9:0] -> d[11:2]
11
A/D [8:0] -> d[11:3]
Reserved
3
2
VsynPol
HsynPol
Assert to force the vsync signal to
generate a logic 0 during a frame
readout (Level Mode), or a nega-
tive pulse at the end of a frame
readout (Pulse Mode) . Clear (the
default) to force the vsync signal
to generate a logic 1 during a
frame readout (Level Mode), or a
negative pulse at the end of a
frame readout (Pulse Mode) .
Assert to force the hsync signal to
generate a logic 0 during a row
readout (Level Mode), or a nega-
tive pulse at the end of a row
readout (Pulse Mode) . Clear (the
default) to force the hsync signal
to generate a logic 1 during a row
readout (Level Mode), or a nega-
tive pulse at the end of a readout
(Pulse Mode) .
1
0
OddEvenEn
TriState
Assert to force the vsync pin to act
as an odd/even field indicator.
Clear (the default) to force the
vsync pin to act as a vertical syn-
chronization signal.
Assert to tri-state all output signals
(data and control) on the digital
video port. Clear (default) to
enable all signals (data and con-
trol) on the digital video port.
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相关PDF资料
KAC-9627 IC SENSOR IMAGE VGA 48CLCC
KB-A100SRW LIGHT BAR 660NM RED 8.89X3.81MM
KB-B100SRW LIGHT BAR 660NM RED 19.05X3.81MM
KB-C100SRW LIGHT BAR 660NM RED 8.89X8.89MM
KB-D100SRW LIGHT BAR 660NM RED 8.89X3.81MM
KB-E100SRW LIGHT BAR 660NM RED 8.89X3.81MM
KB-F100SRW LIGHT BAR 660NM RED 19.05X3.81MM
KB-G100SRW LIGHT BAR 660NM RED 8.89X8.89MM
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